The present invention relates to a non-volatile semiconductor memory cell having a metal oxide dielectric, in particular to a memory cell for an EPROM, an EEPROM or a FLASH-EPROM memory cell, and to a method for fabricating such a memory cell.
Non-volatile semiconductor memory cells that are known, for example, from the publication by Kevin J. O""Coner et al., xe2x80x9cA Novel CMOS Compatible Stacked Floating Gate using TiN as a Control Gatexe2x80x9d, 1997 symposium on VLSI Technology Digest of Technical Papers, pages 61-62 and that are used in EPROM, EEPROM and FLASH-EPROM memories, usually include a semiconductor substrate, an insulating tunnel oxide layer, a conductive floating-gate layer, an insulating dielectric layer and a conductive control-gate layer. To store information, charges are introduced from a channel region, which is formed in the semiconductor substrate, via the tunnel oxide layer into the floating-gate layer. Methods for introducing the charges into the floating-gate layer are, for example, injection of hot charge carriers, channel injection and Fowler-Nordheim tunneling.
Furthermore, the document Godberg, G. A.: xe2x80x9cNovel dielectrics for non-volatile memory devicesxe2x80x9d, dissertation from the University of Warwick, Coventry UK, 1978, discloses a non-volatile semiconductor memory cell that has a double dielectric as an intermediate layer and that has a dielectric layer containing a metal oxide layer, such as for example titanium oxide, tantalum pentoxide, niobium pentoxide and zirconium pentoxide. However, this arrangement does not use a conductive floating-gate layer.
The dielectric layer which lies between the floating-gate layer and the control-gate layer is of particular importance for retention of the charges stored in the floating-gate layer. This dielectric layer usually includes an xe2x80x9cONOxe2x80x9d layer, i.e. a layer sequence including oxide, nitride, oxide. It is preferable to use a layer sequence of approximately 4 nm SiO2, 7 nm of Si3N4 and 4 nm of SiO2 for this ONO layer.
U.S. Pat. No. 5,836,772 discloses an improved ONO layer in which the nitride layer that is used is thinner than the adjoining oxide layers.
FIG. 7 is a diagrammatic band diagram for a conventional non-volatile semiconductor memory cell having an ONO layer sequence between floating-gate layer and control-gate layer. In FIG. 7, reference numeral 1s denotes a semiconductor substrate, 3s denotes an insulating tunnel oxide layer, 4s denotes a conductive floating-gate layer, which preferably consists of poly-Si, 10s denotes an insulating dielectric layer, and 7 denotes a conductive control-gate layer which once again consists of poly-Si. The dielectric layer 10s includes a Si3N4 layer 10n which lies between two SiO2 layers 10o and forms the so-called ONO layer.
A drawback of using ONO layers of this type for the dielectric layer 10s is the relatively great thickness of at least 15 nm. This minimum thickness is necessary in order to ensure the required charge retention in the floating-gate layer 4s, making large-scale integration more difficult. Furthermore, this minimum thickness of approximately 15 nm has an adverse effect on the coupling factor in the non-volatile semiconductor memory cell, which is the decisive factor in determining both the read currents (and therefore the access times) and the level of the voltages that are required to erase and write the semiconductor memory cells. Therefore, the coupling factor can only be improved by enlarging the floating-gate regions, which in turn has an adverse effect on the integration density of semiconductor memory cells of this type.
U.S. Pat. No. 4,115,914, which forms a generic document, discloses a non-volatile semiconductor memory cell having a semiconductor substrate, an insulating tunnel oxide layer, a conductive floating-gate layer, an insulating dielectric layer and a conductive control-gate layer. The dielectric layer has at least one metal oxide layer including, for example, TiO2.
Furthermore, Japanese Patent Application JP 07 135202 discloses a semiconductor device and an associated fabrication method in which, to level an intermediate insulation layer, a tungsten layer is deposited as a dielectric layer and is then oxidized in order to form a WO3 layer.
U.S. Pat. No. 5,998,264, which is a later publication, discloses a flash memory cell and an associated fabrication method in which a dielectric, such as for example TiO2, is used for the dielectric layer between the floating gate and the control electrode. In addition, a dielectric with a high dielectric constant, such as for example WN or TiN, is used for the floating-gate layer.
It is accordingly an object of the invention to provide a non-volatile semiconductor memory cell and a method for fabricating the memory cell which overcome the above-mentioned disadvantages of the prior art apparatus and methods of this general type.
In particular, it is an object of the invention to provide a non-volatile semiconductor memory cell and a corresponding fabrication method in which both an improved integration density and a reduction in the required control voltages are possible.
With the foregoing and other objects in view there is provided, in accordance with the invention, a non-volatile semiconductor memory cell, including: a semiconductor substrate; an insulating tunnel oxide layer; a conductive floating-gate layer; an insulating dielectric layer including at least one metal oxide layer and at least one Si3N4 layer enclosing the metal oxide layer; and a conductive control-gate layer. The metal oxide layer is made of a material selected from the group consisting of WOx, where x=2 to 3, and TiO2.
In accordance with an added feature of the invention, the floating-gate layer includes a poly-Si layer.
In accordance with an additional feature of the invention, the floating-gate layer includes a layer selected from the group consisting of a TiN layer and a WN layer.
In accordance with another feature of the invention, the floating-gate layer includes a layer selected from the group consisting of a TiN layer and a WN layer.
In accordance with a further feature of the invention, the dielectric layer has a thickness that is greater than 15 nm.
In accordance with a further added feature of the invention, the floating-gate layer has a thickness in a range from 5 nm to 50 nm.
With the foregoing and other objects in view there is also provided, in accordance with the invention, a method for fabricating a non-volatile semiconductor memory cell, that includes steps of: a) forming active regions in a semiconductor substrate; b) forming a tunnel oxide layer; c) depositing a floating-gate layer; d) depositing a metal-containing layer that includes a material selected from the group consisting of a metal and a metal compound; e) etching the metal-containing layer and the floating-gate layer; f) oxidizing the metal-containing layer and exposed side regions of the floating-gate layer to form a dielectric layer; g) depositing a control-gate layer; and h) etching the control-gate layer, the dielectric layer, and the floating-gate layer.
In accordance with an added mode of the invention, in step c) a TiN layer is deposited; and in step d) a Ti layer is deposited.
In accordance with an additional mode of the invention, in step c) a poly-Si layer is deposited; and in step d) a WOx layer is deposited, where x=2 to 3.
In accordance with another mode of the invention, in steps c) and d) a common tungsten-containing layer is deposited; and in step f) the oxidizing is performed until an oxidized partial layer of the tungsten-containing layer forms the dielectric layer and an unoxidized partial layer of the tungsten-containing layer forms the floating-gate layer.
In accordance with an added mode of the invention, there is provided a step of i) forming an insulating intermediate layer on the surface of the control-gate layer.
In particular, the use of an Si3N4 layer that encloses the metal oxide layer enables leakage currents to be reduced further and enables a higher integration density to be achieved.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a non-volatile semiconductor memory cell having a metal oxide dielectric, and method for its fabrication, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.